Quartus II support for Verilog HDL is described for the following categories of Verilog HDL constructs. These sections match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.
Quartus II Support for Verilog 2001
| IEEE Section: | Description: |
|---|---|
| 3 | Data Types |
| 4 | Expressions |
| 6 | Assignments |
| 7 | Gates & Switches |
| 8 | User Defined Primitives |
| 9 | Behavioral Modeling |
| 10 | User Defined Tasks & Functions |
| 11 | Disable Statements |
| 12 | Hierarchical Structures |
| 13 | Specify Blocks |
| 14 | System Tasks & Functions |
| 16 | Compiler Directives |
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