Hierarchical Structures (Quartus II Verilog HDL Support)

Hierarchical Structures

Quartus^® II support for hierarchical structures is described below. Section numbers match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

Section	Verilog HDL Construct	Quartus II Support Note (1)
12.1	Modules	Supported.
12.2	Parameter Value	Supported as defined in subsections Overriding Statements 12.2.1 and 12.2.2.
12.2.1	Defparam Statements	Supported.
12.2.2	Module Instance Parameter Value Assignment Statements	Supported.
12.3	Ports	Supported.
12.4	Hierarchical Names	Supported for Defparam Statements in Module Instantiations for parameterized functions. Hierarchical names in Defparam Statements can contain only two hierarchical levels.

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