Verilog HDL

Expressions

Quartus® II support for expressions is described below. Section numbers match those in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

Section Verilog HDL Construct Quartus II Support     Note (1)
4.1 Operators Supported as defined below.
4.1.5 Arithmetic Operators Supported.
4.1.7 Relational Operators Supported.
4.1.8 Equality Operators Supported except for the === and !== operators.
4.1.9 Logical Operators Supported.
4.1.10 Bit-Wise Operators Supported.
4.1.11 Reduction Operators Supported.
4.1.12 Shift Operators Supported.
4.1.13 Conditional Operators Supported.
4.1.14 Concatenations Supported.
4.1.15 Event or Operators Supported.
4.2 Operands Supported as defined below.
4.2.1 Bit-Select and Part-Select Operands Supported.
4.2.2 Memory Addressing Supported.
4.2.3 String Operands Supported.
4.3 Minimum, Typical, and Maximum Delay Expressions Not supported.


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