See Also

Parameterized dual-clock FIFO megafunction. The lpm_fifo_dc function uses mega RAMs or M4K or M512 memory blocks in Stratix^™ and Stratix^™ GX devices, M4K memory blocks in Cyclone^™ devices, Embedded System Blocks (ESB) in APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, and Mercury^™ devices, Embedded Array Blocks (EAB) in ACEX^® 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX^® 6000, MAX^® 3000, and MAX 7000 devices or if the USE_EAB parameter is set to "OFF". If you need extra features you may use the dcfifo megafunction. Altera^® strongly recommends using synchronous rather than asynchronous RAM functions.

The Quartus® II Compiler automatically implements suitable portions of this function in mega RAMs or M4K or M512 memory blocks in Stratix and Stratix GX devices, in M4K memory blocks in Cyclone devices, in ESBs in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, and in EABs in ACEX 1K and FLEX 10KE devices. The Compiler automatically implements this function in logic cells in FLEX 6000, MAX 3000, and MAX 7000 devices.

Altera also recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager.

The synchronization and internal logic in lpm_fifo_dc may cause the information in the wrempty, wrfull, wrusedw[], rdempty, rdfull, and rdusedw[] ports to be delayed by one clock cycle of latency.

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions
• Truth Table/Functionality
• Resource Usage

FUNCTION lpm_fifo_dc (data[LPM_WIDTH-1..0], rdreq, wrreq, rdclock, wrclock, aclr)
   WITH (LPM_WIDTH, LPM_NUMWORDS, LPM_WIDTHU, LPM_SHOWAHEAD, 
      UNDERFLOW_CHECKING, OVERFLOW_CHECKING,ALLOW_RWCYCLE_WHEN_FULL, 
      USE_EAB, DELAY_RDUSEDW, DELAY_WRUSEDW, RDSYNC_DELAYPIPE, WRSYNC_DELAYPIPE)
   RETURNS (q[LPM_WIDTH-1..0], rdempty, rdfull, wrempty, wrfull, 
      rdusedw[LPM_WIDTHU-1..0], wrusedw[LPM_WIDTHU-1..0]);

COMPONENT lpm_fifo_dc
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_WIDTHU: POSITIVE := 1;
      LPM_NUMWORDS: POSITIVE;
      LPM_SHOWAHEAD: STRING:= "OFF";
      LPM_TYPE: STRING := "LPM_FIFO_DC";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      wrclock, rdclock, wrreq, rdreq: IN STD_LOGIC;
      aclr: IN STD_LOGIC := '0';
      wrfull, rdfull, wrempty, rdempty: OUT STD_LOGIC;
      wrusedw, rdusedw: OUT STD_LOGIC_VECTOR(LPM_WIDTHU-1 DOWNTO 0)
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

LIBRARY lpm;
USE lpm.lpm_components.all;

INPUT PORTS

OUTPUT PORTS

Parameter	Type	Required	Description
LPM_WIDTH	Integer	Yes	Width of data[] and q[] ports.
LPM_WIDTHU	Integer	Yes	Recommended value is CEIL(LOG2(LPM_NUMWORDS)). Width of the rdusedw[] and wrusedw[] ports.
LPM_NUMWORDS	Integer	Yes	Number of words stored in memory, which is usually a power of 2. The last three words of the lpm_fifo_dc may not be available for writing because of the synchronization pipelines between the two Clock schemes. These pipelines are intended to avoid internal metastability. Because of these pipelines, information available to one Clock scheme regarding when reads and writes occur may be temporarily unavailable to the other Clock. The wrfull and rdfull ports of a lpm_fifo_dc must be raised high slightly before the lpm_fifo_dc is completely full, in order to avoid overshooting the top of the fifo. This process may cause several words at the end of the fifo to become unavailable. Depending on the rate you are writing to the fifo, the wrfull and rdfull ports may go high with three words remaining, with two words remaining, or with one word remaining in the fifo. However, this process is necessary both to accommodate the clock synchronization and to ensure overshoot does not take place. If you need to maintain a specific number of words, you may want to specify a number for the LPM_NUMWORDS parameter that is up to three words greater than the amount you believe is needed.
LPM_SHOWAHEAD	String	No	Allows the data to appear on q[] immediately without asserting rdreq explicitly. Values are "ON" or "OFF" (the default is "OFF"). Specifying "ON" for LPM_SHOWAHEAD may reduce performance.
LPM_HINT	String	No	Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
OVERFLOW_CHECKING	String	No	Altera-specific parameter. Disables the overflow-checking logic when set to "OFF", so that wrfull is no longer checked for wrreq. Values are "ON" or "OFF" (the default is "ON"). Writing to a full lpm_fifo_dc gives unpredictable results.
UNDERFLOW_CHECKING	String	No	Altera-specific parameter. Disables the underflow-checking logic when set to "OFF", so that rdempty is no longer checked for rdreq. Values are "ON" or "OFF" (the default is "ON"). Reading an empty lpm_fifo_dc gives unpredictable results.
DELAY_RDUSEDW	Integer	No	Altera-specific parameter. Any integer greater than or equal to 0. Specifies the number of register stages that are added internally to the rdusedw[] port. The default value of 1 adds a single register stage to the output to improve its performance. This parameter is not available for simulation with other EDA simulators.
DELAY_WRUSEDW	Integer	No	Altera-specific parameter. Any integer greater than or equal to 0. Specifies the number of register stages that are added internally to the wrdusedw[] port. The default value of 1 adds a single register stage to the output to improve its performance. This parameter is not available for simulation with other EDA simulators.
RDSYNC_DELAYPIPE	Integer	No	Altera-specific parameter. Specifies the number of register stages that are added internally for synchronization from the write control logic to the read control logic. The default value of 3 provides good insurance against the possibility of internal metastability when rdclock and wrclock are unrelated. This parameter is not available for simulation with other EDA simulators.
WRSYNC_DELAYPIPE	Integer	No	Altera-specific parameter. Specifies the number of register stages that are added internally for synchronization from the read control logic to the write control logic. The default value of 3 provides good insurance against the possibility of internal metastability when rdclock and wrclock are unrelated. This parameter is not available for simulation with other EDA simulators.
USE_EAB	String	No	Altera-specific parameter. Values are "ON", "OFF", and "UNUSED". Setting the USE_EAB parameter to OFF prevents the Quartus II software from using ESBs to implement the logic in APEX 20K, APEX II, ARM-based Excalibur, and Mercury devices, or EABs in ACEX 1K and FLEX 10KE devices; it can use only flipflops or latches. (The "ON" setting is not useful in memory functions: the Quartus II software automatically implements memory functions in ESBs or EABs by default.) This parameter is not available for simulation with other EDA simulators and for FLEX 6000, MAX 3000, MAX 7000, Stratix, and Stratix GX devices.

The lpm_fifo_dc function represents memory with synchronous inputs and/or outputs.

Synchronous Memory Operations
rdclock rdreq wrclock wrreq aclr Function X X X X H Resets the lpm_fifo_dc to empty. L X X L No change (requires positive clock edge). H X X L Read from the lpm_fifo_dc (if not empty). X X L L No change. X X H L Write to the lpm_fifo_dc (if not full).

Uses one embedded cell per data output bit for ACEX 1K, APEX 20K, APEX II, ARM-based Excalibur, FLEX 10KE, Mercury, Stratix, and Stratix GX devices; however, in FLEX 6000, MAX 3000, and MAX 7000 devices, or if the USE_EAB parameter is set to "OFF", uses one logic cell per memory bit.

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