A synchronous, true dual-port memory block, with registered inputs and optionally registered outputs, available in Cyclone^™, Stratix^™, and Stratix^™ GX devices. The M4K block is useful for storing processor code, implementing lookup schemes, and implementing large memory applications. Each block is a 128 × 36 RAM block and contains 4,608 programmable bits, including parity bits. The M4K block can be configured as true dual-port, dual-port, and single-port RAM, FIFO buffers, and ROM, and you can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to pre-load the memory contents when the M4K memory block is configured as a RAM or ROM.

When implementing memory in Cyclone, Stratix, and Stratix GX devices, the M4K memory block can be configured in any of the following sizes:

Operation Mode	M4K Memory Block Size
Single-port and ROM	128 × 36 256 × 18 512 × 9 1024 × 4 2048 × 2 4096 × 1
Dual-port	Write × M / Read × N W × Y / R × Z M, N= 1, 2, 4, 8, 16, or 32 Y, Z= 9, 18, or 36
True dual-port	port A × M / port B × N3 A × Y / B × Z3 M, N = 1, 2, 4, 8, or 16 M > N Y, Z = 9 or 18 Y > Z

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