See Also

In VHDL, constants, signals, variables, functions, and parameters can be declared with a type that defines and restricts their characteristics. Each object can hold or return values of these types. Each type has a set of values and a set of operations. When objects are assigned to a type, they are restricted to the values and operations for that type.

Altera^® recommends using the following types:

• STD_LOGIC and STD_LOGIC_VECTOR types. These types are defined in IEEE Std 1164-1993. A copy of the std_logic_1164 package, which includes these types, is provided in the ieee library in the \quartus\libraries\vhdlnn\ieee directory, where nn is "87" or "93".

• BIT and BIT_VECTOR types. These types are defined in IEEE Std 1076-1987. A copy of the standard package, which includes these types, is provided in the std library in the \quartus\libraries\vhdlnn\std directory, where nn is "87" or "93".

• SIGNED and UNSIGNED types. These types are provided in the std_logic_arith, numeric_std, and numeric_bit packages in the ieee library in the \quartus\vhdlnn\ieee directory, where nn is "87" or "93".

Altera does not recommend using both BIT and STD_LOGIC types in the same VHDL Design File (.vhd). Doing so will require you to add conversion functions, which could lead to unnecessary confusion and coding.

This section includes the following topics:

• Using SIGNED & UNSIGNED Types
• Using Conversion Functions
• Using Arithmetic & Relational Operators

For more information, see "Section 3: Types" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.

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