Megafunction

lpm_ff (D- or T-type Flipflop) Megafunction

Parameterized flipflop megafunction. The lpm_ff function contains features that are not available in the DFF, DFFE, DFFEA, TFF, and TFFE primitives, such as synchronous or asynchronous set, clear, and load inputs.

Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION lpm_ff (data[LPM_WIDTH-1..0], clock, enable, sclr, sset, sload, aclr, aset, aload)
   WITH (LPM_WIDTH, LPM_AVALUE, LPM_SVALUE, LPM_FFTYPE)
   RETURNS (q[LPM_WIDTH-1..0]);

 

VHDL Component Declaration:

 
COMPONENT lpm_ff
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_AVALUE: STRING := "UNUSED";
      LPM_SVALUE: STRING := "UNUSED";
      LPM_PVALUE: STRING := "UNUSED";
      LPM_FFTYPE: STRING := "DFF";
      LPM_TYPE: STRING := "LPM_FF";
      LPM_HINT: STRING := "UNUSED");
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      clock: IN STD_LOGIC;
      enable: IN STD_LOGIC := '1';
      sload, sclr, sset, aload, aclr, aset: IN STD_LOGIC := '0';
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
data[] No T-type flipflop: Toggle enable
D-type flipflop: Data input		 Input port LPM_WIDTH wide. If the data[] input is not used, at least one of the aset, aclr, sset, or sclr ports must be used. Unused data inputs default to GND.
clock Yes Positive-edge-triggered clock.
enable No Clock enable input. Default = 1.
sclr No Synchronous clear input. If both sset and sclr are used and both are asserted, sclr is dominant. The sclr signal affects the output q[] values before polarity is applied to the ports.
sset No Synchronous set input. Sets q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1's. If both sset and sclr are used and both are asserted, sclr is dominant. The sset signal affects the output q[] values before polarity is applied to the ports.
sload No Synchronous load input. Loads the flipflop with the value on the data input on the next active clock edge. Default = 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high (1) or unconnected. The sload port is ignored when the LPM_FFTYPE parameter is set to "DFF".
aclr No Asynchronous clear input. If both aset and aclr are used and both are asserted, aclr is dominant. The aclr signal affects the output q[] values before polarity is applied to the ports.
aset No Asynchronous set input. Sets q[] outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q[] outputs to all 1s.
aload No Asynchronous load input. Asynchronously loads the flipflop with the value on the data input. Default = 0. If aload is used, data must be used.

OUTPUT PORTS

Port Name Required Description Comments
q[] Yes Data output from D or T flipflops. Output port LPM_WIDTH wide.

 

Parameter Descriptions:
Parameter Type Required Description
LPM_WIDTH Integer Yes Width of the data[] and q[] ports.
LPM_AVALUE Integer / String No Constant value that is loaded when aset is high. If omitted, defaults to all 1s. The LPM_AVALUE parameter is limited to a maximum of 32 bits. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_SVALUE Integer / String No Constant value that is loaded on the rising edge of clock when sset is high. If omitted, defaults to all 1s. Altera recommends that you specify this value as a decimal number for AHDL designs.
LPM_FFTYPE String No Values are "DFF", "TFF", and "UNUSED". Type of flipflop. If omitted, the default is "DFF". When the LPM_FFTYPE parameter is set to "DFF", the sload port is ignored.
LPM_HINT String No Allows you to specify Altera-specific parameters in VHDL Design Files (.vhd). The default is "UNUSED".
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL Design Files.

 

Truth Table/Functionality: (TFF Example)
Inputs Outputs
aclr aset enable clock sclr sset sload Q[LPM_WIDTH-1..0]
1 x x x x x x 000...
0 1 x x x x x 111... or LPM_AVALUE
0 0 0 x x x x q[LPM_WIDTH-1..0]
0 0 1 Rising Edge 1 x x 000...
0 0 1 Rising Edge 0 1 x 111... or LPM_SVALUE
0 0 1 Rising Edge 0 0 1 data[LPM_WIDTH-1..0]
0 0 1 Rising Edge 0 0 0 q[LPM_WIDTH-1..0]

 

Resource Usage:

Uses one logic cell per bit.

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