altmemmult Megafunction

altmemmult (Memory Multiplier) Megafunction

Parameterized memory multiplier megafunction. The altmemmult megafunction enables RAM-based signed or unsigned multiplier functions. The altmemmult megafunction is available for Cyclone^™, Stratix^™, and Stratix^™ GX devices only.

Altera^® recommends instantiating this function as described in Using the MegaWizard^® Plug-In Manager.

This topic contains the following information:

AHDL Function Prototype (also applies to Verilog HDL)
VHDL Component Declaration
VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
Port Descriptions
Parameter Descriptions

AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION altmemmult (clock, coeff_in[WIDTH_C-1..0], data_in[WIDTH_D-1..0], sclr, select[WIDTH_S-1..0],
      sload_data, sload_coeff )
   WITH (WIDTH_D, WIDTH_C, WIDTH_S = 1, WIDTH_R, COEFFICIENT0, TOTAL_LATENCY, MAX_CLOCK_CYCLES_PER_RESULT,
      RAM_BLOCK_TYPE, DATA_REPRESENTATION )
   RETURNS (result[WIDTH_R-1..0], result_valid, load_done);

VHDL Component Declaration:

COMPONENT altmemmult
   GENERIC
      (WIDTH_D                     : INTEGER;
      WIDTH_C                      : INTEGER;
      WIDTH_S                      : INTEGER := 1;
      WIDTH_R                      : INTEGER;
      NUMBER_OF_COEFFICIENTS       : INTEGER := 1;
      TOTAL_LATENCY                : INTEGER;
      MAX_CLOCK_CYCLES_PER_RESULT  : INTEGER := 1;
      RAM_BLOCK_TYPE               : STRING  := "AUTO" ;
      COEFFICIENT0                 : INTEGER;
      DATA_REPRESENTATION          : STRING  := "SIGNED";
      COEFF_REPRESENTATION         : STRING  := "SIGNED");

   PORT (clock, sclr, sload_data, sload_coeff  : IN STD_LOGIC_VECTOR;
        coeff_in                               : IN STD_LOGIC_VECTOR(WIDTH_C-1..0);
        data_in                                : IN STD_LOGIC_VECTOR(WIDTH_D-1..0);
        select                                 : IN STD_LOGIC_VECTOR(WIDTH_S-1..0);
        result_valid, load_done                : OUT STD_LOGIC_VECTOR;
        result                                 : OUT STD_LOGIC_VECTOR(WIDTH_R-1..0));

END COMPONENT;

VHDL LIBRARY-USE Declaration

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

Port Descriptions:

INPUT PORTS

Port Name	Required	Description	Comments
`clock`	Yes	Clock input port for the multiplier.
`coeff_in[]`	No	Coefficient input port for the multiplier.	Input port `[WIDTH_C-1..0]` wide. The current version of the Quartus^® II software does not support the `sload_coeff` port.
`data_in[]`	Yes	Data input port to the multiplier.	Input port `[WIDTH_D-1..0]` wide.
`sclr`	No	Synchronous clear input.	If unused, the default value is active high.
`select[]`	No	Fixed coefficient selection.	Input port `[WIDTH_S-1..0]` wide. If only one coefficient exists, the `select[]` input port is not available. The current version of the Quartus II software does not support the `sload_coeff` port.
`sload_data`	No	Signal that specifies new multiplication operation and cancels any existing multiplication operation.	If the `MAX_CLOCK_CYCLES_PER_RESULT` parameter has a value of `1`, the `sload_data` input port is ignored.
`sload_coeff`	No	Replaces the current selected coefficient value with the value specified in the `coeff_in` input port.	The current version of the Quartus II software does not support the `sload_coeff` port.

OUTPUT PORTS

Port Name	Required	Description	Comments
`result[]`	Yes	Multiplier output port.	Output port `[WIDTH_R-1..0]` wide.
`result_valid`	Yes	Indicates when the output is the valid result of a complete multiplication.	If the `MAX_CLOCK_CYCLES_PER_RESULT` parameter has a value of `1`, the `result_valid` output port is not used.
`load_done`	No	Indicates when the new coefficient has finished loading.	The current version of the Quartus II software does not support the `load_done` port.

Parameter Descriptions:

Parameter	Type	Required	Comments
`WIDTH_D`	Integer	Yes	Specifies the width of the `data_in[]` port.
`WIDTH_C`	Integer	Yes	Specifies the width of the `coeff_in[]` port.
`NUMBER_OF_COEFFICIENTS`	Integer	No	Specifies the number of coefficients that are stored in the lookup table.
`WIDTH_S`	Integer	No	Specifies the width, in bits, of the `select[]` port.
`WIDTH_R`	Integer	Yes	Specifies the width, in bits, of the `result[]` port.
`COEFFICIENT0`	Integer	Yes	Specifies value of the first fixed coefficient.
`COEFFICIENT1..COEFFICIENTn`	Integer	Yes	Specifies additional coefficients in the lookup table.
`TOTAL_LATENCY`	Integer	Yes	Specifies the total number of clock cycles from the start of a multiplication to the time the result is available at the output.
`MAX_CLOCK_CYCLES_PER_RESULT`	Integer	No	Specifies the number of clock cycles per result.
`DATA_REPRESENTATION`	String	No	Specifies whether the `data_in[]` input port is signed or unsigned.
`COEFF_REPRESENTATION`	String	No	Specifies whether the `coeff_in[]` input port and the pre-loaded coefficients are signed or unsigned.
`RAM_BLOCK_TYPE`	String	No	Specifies the ram block type. Values are `"AUTO"`, `"SMALL"`, `"MEDIUM"`, `"M512"`, and `"M4K"`. If omitted, the default is `AUTO`.

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