A file which contains an instantiation of a top-level design entity for a design and simulation input vectors and simulation output vectors. A test bench file can be a standard Verilog Design File (with the extension .v or .verilog), a VHDL Design File (with the extension .vhd or .vhdl), or one of the following types that can be generated with the Quartus^® II software:

• Verilog Test Bench File (.vt)

• VHDL Test Bench File (.vht)