A design entity that can be used together with gate and flipflop primitives and/or megafunctions in Quartus^® II design files.

Entities include the following:

• user AHDL macrofunctions

• VHDL entity-architecture design units

• Verilog HDL modules

• EDIF cells inside an EDIF design

• user schematic (or block diagram) macrofunctions

• LPM functions

• megafunctions

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