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You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the Synopsys^® FPGA Express and Quartus^® II software. This procedure shows only how to instantiate an LVDS function using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.

1. If you have not already done so, proceed to Set Up the FPGA Express Working Environment.

2. If you have not already done so, proceed to Create a Design for Use with the FPGA Express Software.

3. Open the MegaWizard^® Plug-In Manager (Tools menu) and specify appropriate options for the megafunction you want to instantiate.

The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions, as well as Altera^® megafunctions.

Refer to the following example to create a Verilog HDL custom megafunction variation of the altlvds_rx function:

• Example of Creating a Verilog HDL Custom Variation of the altlvds_rx Function.

4. To prepare the Verilog  HDL design for synthesis with the FPGA Express or FPGA Compiler II software, you must specify that the tool should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The software then makes the correct connections to the ports in the EDIF netlist file (.edf). The Quartus II software reads in the EDIF netlist file as an EDIF Input File (.edf) and processes the instantiated megafunction. To treat the design file for the megafunction as a "black box," refer to the following example:

• Example of Creating a "Black Box" for a Custom Megafunction Variation Using the FPGA Express Software




The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the EDIF Input File or added to the Quartus II project.

5. If necessary, perform a functional simulation with the VCS software or another simulation tool. Refer to the following example for a sample script that you can use to perform a functional simulation:

• Example of Performing a Functional Simulation of a Verilog HDL Design with a Custom Megafunction Variation in the ModelSim^® Software.

6. Proceed to Generate EDIF Netlist Files with the FPGA Express^® Software.

7. If you have not already done so, create a new project or open an existing project.

8. Compile the design in the Quartus II software.

9. If necessary, proceed to Perform a Timing Simulation with the ModelSim Software or simulate the design with another Verilog HDL simulation tool.

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